1. Field of the Invention
Embodiments of the present invention generally relate to a method for forming a copper interconnect on a substrate.
2. Description of the Related Art
Metallization for sub-quarter micron sized features is a foundational technology for present and future generations of integrated circuit manufacturing processes. In devices such as ultra large scale integration-type devices, i.e., devices having integrated circuits with more than a million logic gates, the multilevel interconnects that lie at the heart of these devices are generally formed by filling high aspect ratio interconnect features with a conductive material, such as copper or aluminum, for example.
One method for forming vertical and horizontal interconnects is by a damascene or dual damascene method. In the damascene method, one or more dielectric materials, such as low k dielectric materials, are deposited and pattern etched to form the vertical interconnects, e.g., vias, and horizontal interconnects, e.g., lines. Conductive materials, such as copper containing materials, and other materials, such as barrier layer materials used to prevent diffusion of copper containing materials into the surrounding low k dielectric, are then inlaid into the etched pattern. Any excess copper containing materials and excess barrier layer material external to the etched pattern, such as on the field of the substrate, is then removed.
However, low k dielectric materials generally have low mechanical strength, making it difficult for the low k dielectric material to withstand further processing, such as planarization by chemical mechanical processing. In addition, damascene processes generally result in structures that exhibit stress and electromigration from the copper interconnect to the low k dielectric. Furthermore, low k dielectric materials are often porous and susceptible to interlayer diffusion of conductive materials, such as copper, which can result in the formation of short-circuits and device failure.
Therefore, there remains a need for an improved process for depositing barrier materials to prevent copper migration into surrounding low k dielectric materials.
Embodiments of the invention generally include a method for processing a substrate. The method generally includes forming a copper interconnect in a sacrificial layer deposited on the substrate by patterning the sacrificial layer to form an interconnect and filling the interconnect with copper. The method additionally includes removing at least a portion of the sacrificial layer upon copper interconnect formation, depositing a barrier layer on the copper interconnect, and forming a dielectric layer on the substrate after depositing the barrier layer to insulate the copper interconnect.
Embodiments of the invention further include a method for processing multiple layers of a substrate. The method generally includes forming a first copper interconnect in a sacrificial layer deposited on the substrate by patterning the sacrificial layer to form an interconnect and filling the interconnect with copper. The method then includes repeating the steps to form a second copper interconnect, removing the sacrificial layers from the first and second copper interconnect, depositing a barrier layer adjacent the copper interconnects, and depositing a dielectric layer adjacent the barrier layer.